First steps to customize pyrpl on the RedPitaya. Does it compile?

Install Vivado 2015.4 on Windows laptop. Clone https://github.com/lneuhaus/pyrpl.git In the directory pyrpl/pyrpl/fpga run this command in windows power shell:

C:\Xilinx\Vivado\2015.4\bin\vivado.bat -nolog -nojournal -mode batch -source red_pitaya_vivado.tcl

This created the files:

/fpga/red_pitaya.bin

pyrpl/fpga/project/pyrpl.srcs/sources_1/bd/system/hw_handoff/system.hwh

Installed pynq on a RedPitaya following https://github.com/dspsandbox/Pynq-Redpitaya-125 Trying to load the bitfile gives this error:

File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynqmetadata/frontends/hwh_frontend.py:452, in HwhFrontend._resolve_subordinate_addressing(self) 450 for i in self._root.iter("MEMRANGE"): 451 if i.get("MEMTYPE") == "REGISTER" or i.get("MEMTYPE") == "MEMORY": --> 452 core = self.blocks[i.get("INSTANCE")] 453 port = core.ports[i.get("SLAVEBUSINTERFACE")] 454 if isinstance(port, SubordinatePort): KeyError: 'M_AXI_GP0'