Attached is a block diagram describing the behavior of a DSP system permforming feedback control for the Pound-Drever-Hall (PDH) frequency stabilization technique. This block diagram is based on Liquid Instrument's laser lock box, which we have been using to lock our current cavity.
There are two modes of operation: 'scanning mode' and 'locking mode.' When the toggle (on the right side of the diagram) is down, we are in 'locking mode' and the control loop is closed.
In locking mode there are two main tasks. First, we must obtain the error signal from the incoming photodiode signal by demodulation. We mix the incoming signal with the modulation tone, (with an adjustable phase offset) then we low-pass filter to remove unwanted high-frequency signal coming from the mixing. Then we subtract the desired setpoint from this signal to obtain the error signal. At this location, the error point, we want to be able to take time series of the values. These timeseries will be used to evaluate the characteristics of the loop and to make the transition from scanning mode to locking mode. Next, the error signal is passed through a series of biquad filters (the controller) to create the signal to be sent to the actuators. A constant offset is added to this signal and it is sent out to the actuator.
In scanning mode there is no feedback. Instead, the actuator voltage is swept by the sawtooth generator, and the error signal is monitored at the error point. Using the timeseries of the error signal during this sweep we can adjust the value of the constant offset and toggle the switch, exiting sweep mode and closing the loop.
To meet the requirements of the GQuEST experiement, we want to lock the cavities with a 10kHz unity gain frequency, and a 'low enough' root-mean-squared displacement. We will continue to work to understand what is 'low enough' and how this translates to FPGA specs, but until then here is a list of our best guesses at the approximate desired stats. These are based on the stats of the Moku and a few calculations, some of which are found in this log post and its comments. In particular, as the filter sample rate is increased, the number of bits required for the filter coefficients will increase as well.
Filter sample rate - 25MHz (Moku IIR filters use 40MHz)
ADC/DAC bit count - 16bits (Moku combines a 10 MSa/s, 18-bit ADC and a 5 GSa/s, 10-bit ADC)
Biquad internal bit count - 32bits (Moku uses 48bit filter coefficients)
Total input-output latency - 1us (Moku has around 1us)
Can you add a sampling point before and after the SOS so that I can analize how well they are preforming?
Jeff, this looks good. What about timing stability? How stable do frequencies need to be? For more than one PDH control loop, are the feedback loops independent or do we need them to be synchronized?
Attatched is a good reference on Pound-Drever-Hall stabilization
Attached is a powerpoint by Matt Evans on digital filter implementations, including a low noise second order section.