I'm discussing options with Ryan.
We are purchasing one LXD31k4 board, but notice that latency is not so great for the ADC and DAC on it. For the ADC, the pipeline delay (latency) is 26 clock cycles/300 MHz = 87 nSec and for the DAC the latency is 134 clock cycles/300 MHz = 447 nSec.
He found a low-latency (better than 4 nSec) DAC board AD9740-FMC-EBZ but with only 10 bits. So we need to understand how to make that trade-off between #bits and latency.
This ADC card has 12 cycle latency at 125MHz, (96 nSec) dc-coupled, 16-bit, 4-ch + 1 DAC
https://www.vadatech.com/product.php?product=900&catid_now=0&catid_prev=0#prettyPhoto
but the DAC on that one is the DAC3171 which can run up to 500 MHz for a 26 nSec latency at 14 bits.
Ryan found a discussion board on a low latency solution for ADC => FPGA => DAC (basically what we want!) from 8 years ago - looks like this was their conclusion on which chips to use:
The ADS5400 (1GSPS, 7ns latency) and DAC5670 (2.4 GSPS, 4.42 ns latency) are the lowest latency converters currently available.
Ryan is discussing what it would take to build a custom FMC board with these chips.
So, Ryan suggests these purchases to evaluate our options:
- one LXD31k4
- To have a sub-100ns latency example of standard general purpose I/O solution
- one vadatech 4-ch card
- To have a sub-100ns latency example JESD204B serdes interface solution
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From a RedPitaya discussion board on a fast PDH controller: https://forum.redpitaya.com/viewtopic.php?t=1354
by Nils Roos » Thu Mar 31, 2016 9:17 pm
From the datasheets of the ADC and DAC you can derive some estimates for the expected latency.
The ADC has a pipeline latency of 6 cycles plus some nanoseconds clock to output delay. At 125MHz this gives ~50ns latency from the moment the input is sampled to the moment the data is available at the FPGA. The FPGA's input buffers add one cycle, as do the output buffers, and then there is internal routing which typically comes to <10ns, so without any further processing, you get 26ns additional latency through the FPGA. The DAC has 2 cycles of data input to analog output latency, another 16ns. Thus, you end up with just under 100ns minimum delay from analog input to analog output.
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For reference, RFSoC solutions claim to have about 120 nSec latency, depending on how they are configured. (The sample we tested from Leo did NOT optimize at all for latency)
